Differential amplifiers are commonly employed in electronic devices that use analog circuits. In addition to a variety of discrete circuit applications, differential amplifiers are also used in many integrated devices such as, for example, operational amplifiers. Operational amplifiers have been the most common building blocks in analog and mixed signal circuits because of their high gain, high input impedance, high power supply noise rejection and other special characteristics. With their high gain property, one of their many applications is to amplify very small and weak signals to larger ones.
The growing demand for mobile or portable electronic equipment or devices has increased the need to produce simple, lightweight, energy-efficient electronic equipment, which has resulted in an increased demand for low-power operational amplifiers. However, there are some limitations for physical implementation of operational amplifiers, such as signal-to-noise ratio (SNR), offset voltage, and common-mode voltage range.
Generally speaking, to reduce the power consumption of an operational amplifier, the operational amplifier must be operated at relatively low supply voltages. Unfortunately, as the supply voltage is reduced, the useful dynamic input range and output range of the operational amplifier is reduced. In general, the operating range of the input terminals of an operational amplifier depends on the input stage configuration of the operational amplifier. As is well known, the operating range or dynamic range of the input terminals of a differential amplifier is commonly referred to as a common-mode input range (CMR). In the case of an operational amplifier buffer circuit such as, for example, a voltage follower, the CMR of the operational amplifier determines the dynamic range of the buffer inputs. A differential amplifier that provides a CMR substantially equal to the voltage drop across the supply terminals of the differential amplifier is commonly referred to as a rail-to-rail CMR differential amplifier.
FIG. 1 shows a fully differential input stage 100 which is commonly used in an operational amplifier. NMOS devices MN1 and MN2 are ideally identical, as are the PMOS devices MP1 and MP2. MP1 and MP2 are biased by a current mirror with bias voltage Vbp, so each PMOS has same amount of current. In a fully balanced condition, MN1 and MN2 with the same DC voltage at IN an IP have the same amount of current. MN1 and MN2's currents are provided by MN3 which is mirrored by MN4 with bias voltage Vbn. With fixed length, the width of MN3 is two times that of MH4, when MP3, MP1, and MP2 have the same size. Ideally, when input signals IN and IP are at the same DC voltage, output signals ON and OP should have the same DC level which is a known common mode level. In reality, however, because of process variations, the DC potentials of the output signals ON and OP are not the same and not well-defined.
Particularly, because of variations of threshold voltages, mobility, and geometry from original target device specifications during fabrication for PMOS and NMOS type devices, one type of device is stronger than the other one. This unpredictable situation prevents DC outputs ON and OP from being well-defined in the circuit 100 of FIG. 1. When IN and IP are same DC value, voltages of OP and ON both could drift in the same direction to the stronger device (either PMOS or NMOS) to fulfill Kirchoff's current summing law. This drift phenomenon could either degrade amplifier gain or output voltage swing. For example, if stronger devices go into the linear region to maintain the same current as the weaker devices, the output resistance and the gain are significantly reduced.
Furthermore, because of process variations, the same type devices with the same size and bias conditions could be non-identical, in FIG. 1. MN1 and MN2 might not be identical in silicon. Likewise, MP1 and MP2 might not be identical. Mismatches between same type, size, and bias conditions cause unequal amplifier outputs. That is, with equal potential inputs at IP and IN, output voltages at OP and ON are different. When the inputs are the same, the DC difference between the outputs is known as output offset voltage.
Common Mode Feed Back (CMFB) circuits are used to create a well-defined DC common mode output level. A typical CMFB circuit 200 is shown in FIG. 2. To define the desired output voltage level Vcm, two additional differential amplifiers are added. One of the amplifiers consists of CN1, CN2, CN3, and CP1 in circuit 200. The other one consists of CN4, CN5, CN6, and CP1. For each additional amplifier, Vcm provides reference at one input. ON or OP are treated as the other input for the differential amplifier. Each additional amplifier then compares DC value Vera to OP or ON. The differences are averaged by transistor CP1 and biasing voltage Vbp. Vbp ideally adjusts the MP1 and MP2 currents for either addition or subtraction with the same amount of current for both devices, so OP and ON can be adjusted toward Vcm in the same direction. In other words, by sensing the DC output voltage of the output signals OP and ON and by comparing the output signals OP and ON with the desired output DC voltage level Vcm, the output signals OP and ON are adjusted in same direction to be the same as Vent via the feedback loop. However, present CMFB circuits can only correct the common mode output voltage level. That is, they can correct both OP and ON to a Vera value in the same direction. However, they cannot correct the output offset voltage. That is, OP and ON are adjusted toward Vcm in opposite directions, such that while one current or voltage is added, the other's is reduced.
There are several ways to perform offset cancellation, such as auto zero or using a chopper stabilized amplifier. Those ways need the system clock to be involved, and they are classified as discrete type offset cancellation. They cannot cancel offset voltage in a continuous time domain.